The present invention is generally related to comparators in pipelined analog-to-digital converters (ADCs). More particularly, the present invention is related to an apparatus and method for early comparison of the output of a pipelined ADC with an improved delay cell to generate timing control for latching the comparison result.
Analog-to-digital converters (ADCs) can be designed as a series of concatenated pipeline stages that each process one or more bits (e.g. 1-bit, 1.5-bits, 2-bits, etc.) of the conversion process. Each pipeline stage uses a sample-and-hold type of architecture that samples an analog input signal, processes the analog input signal using switched capacitor techniques, and provides the a set of output signals that can be processed by a comparator circuit and any subsequent pipeline ADC stages. During processing, the analog input signal is typically processed according to a transfer curve that uses switched capacitor scaling. The processed quantity corresponds to the conversion of one or more of the most significant bits. The residue of the conversion is passed on to subsequent stages, where further conversion of the analog input signal is provided. All of the comparison results are combined to provide a complete conversion of the analog input signal to a quantized digital value.